1. Field of the Invention
The present invention relates to a probe apparatus used for examining circuits such as semiconductor devices.
2. Description of the Related Art
By use of a conventional probe apparatus, tens to several hundreds of IC chips are examined sequentially one by one as moving the wafer stage in a step-by-step manner at a pitch corresponding to the distance between adjacent IC chips. With such a structure, the probing test is carried out in a subsequent manner, that is, after the test on an IC chip, the test is conducted to the adjacent one, and such an operation is repeated. A great number of pads are formed on an IC chip, and each pad has a rectangular shape with a side of about 20-200 .mu.m. In order to bring a probe into contact with a pad having such an extremely small area, the pad and the probe must be aligned relatively with each other at a high accuracy.
U.S. patent application Ser. No. 922,791, now U.S. Pat. No. 5,321,352 discloses an alignment mechanism (so-called index mechanism) for aligning pads on a chip and probes with each other. In the index mechanism, the wafer stage is moved by fine adjustment in X and/or Y axis in accordance with the position where the tip of the probe is detected.
In the conventional index mechanism, the wafer stage must be aligned on an X-Y plane along both coordinates at a high accuracy, and the driving mechanism becomes complex, large in size, and costly.
Further, the move/stop action of the wafer stage must be repeated frequently for the number of times corresponding to the number of IC chips, thereby being likely to create vibration. Especially, the wafer stage has a small damping capacity due to its heavy weight, and therefore continues to vibrate for a long time after the adjustment is stopped. Consequently, the measurement for the next IC chip must wait until the vibration of the stage is ceased, lowering the throughput. In particular, in the case where the time required to carry out the test per one IC chip (time during which a test signal is transmitted) is short, the ratio of the non-test time (time during which a test signal is not transmitted) to the test cycle time becomes large. There rises a demand of shortening the non-test time.
In the conventional probe apparatus, the probe card circuit is electrically connected to the test head circuit via an insert ring so that a test signal is transmitted to the chip circuit. A pogo pin is set in the insert ring, and as one end of the pogo pin is pressed on a pad of the probe card circuit so as to bring the pogo pin and the pad into electrical contact with each other.
However, a pogo pin includes a great number of parts, and there are a great number of contact interfaces (contact points and contact surfaces) in a current-carrying line. Consequently, each line involves a high electrical resistance, and the electrical resistances of the lines greatly differ from each other. If the resistances of the pogo pins have a large irregularity, the test cannot be performed at a high accuracy. In order to carry out an accurate test, pogo pins of a similar resistance must be carefully selected, and such a selection work is very much complicated.
Further, each pogo pin includes a spring, which makes the inductance thereof high, and a great number of contact interfaces, which makes its insertion loss large. As a result, the measured value of the high-frequency test contains an error, and therefore it is very difficult to achieve an accurate measurement.
Furthermore, each pogo pin is maintaining its electrical contact by means of a spring, and therefore a reflection wave signal is sometimes created at the connecting section between the spring and the pogo pin in the high-frequency test, which is one of the factors which lower the accuracy of the test.